Turning to FIG. 1, a conventional operational amplifier 100 can be seen. The amplifier 100 generally comprises a current mirrors 102 and 108, a differential input pair 104, and an output circuit 106. The current mirrors 102 and 108 generally and respectively comprise transistors Q3 and Q4 (which, as shown, are PMOS transistors) and transistors Q5, Q6, and Q8 (which, as shown, are NMOS transistors). The differential input pair 104 generally comprises transistors Q1 and Q2 (which, as shown, are NMOS transistors or can be NPN transistors that receive input signal INP and INM). The output circuit 106 generally comprises transistors Q7 (which, as shown, are a PMOS transistor and an NMOS transistor, respectively). Additionally, bias voltage BIAS can be applied to the gates of each of transistors Q5, Q6, and Q8. Each of the transistors Q1 through Q8 used also exhibits “normal” behavior, as shown in FIG. 2, where the drain current ID remains relatively constant at large gate-source voltages VGS and increases (almost linearly) at low gate-source voltages VGS.
In FIG. 3, an example of the general operation for amplifier 100 can be seen. For this example, the supply voltage VDD is 1.5V and a voltage of 0.75V is applied as signal INP to transistor Q1. As the voltage for signal INM is ramped, as shown, the output signal VOUT remains at 1.5V until 0.75V is reached. When signal INM reaches 0.75V, output signal VOUT transitions from 1.5V to 0V, allowing amplifier 100 to operate as a comparator.
While the circuitry of FIG. 1 is well-known and has been used for CMOS transistors for many years, there are emerging technologies that have characteristics that may interfere with the desired performance of similar circuits. Turning to FIG. 4, an example of an emerging technology transistor 400 can be seen; namely, transistor 600 is a graphene. An example of the structure and formation of a graphene or carbon nanotube (CNT) transistor can be found in U.S. Pat. No. 7,687,308, which is incorporated herein by reference for all purposes. Alternatively, an example of the structure and formation of a TFET can be found in U.S. Pat. No. 7,812,370, which is incorporated herein by reference.
Here, FIG. 4 shows a simplified example of a cross sectional view of a graphene transistor 400. Similar to CMOS transistors, graphene transistors have a source, drain, and gate. As shown, the transistors 400 is formed over a dielectric layer 404 on a substrate 402. The source and drain electrodes 406 and 408 are opposite one another with the graphene sheet or CNT 410 formed therebetween. The graphene sheet 410 generally operates as the channel of transistor 400, so a gate dielectric layer 412 is formed between the graphene sheet 412 and gate electrode 414 (similar to a CMOS transistor).
The behavior of transistor 400, however, is completely different than CMOS transistor. Transistor 400 operates as an ambipolar transistor, and the I-V characteristics of transistor 400 can be seen in FIG. 5. When comparing FIG. 4 to FIG. 2, it can easily be observed that developing circuitry for ambipolar transistors (i.e., transistor 400) having similar behavior to known circuitry in CMOS (or bipolar) can be challenging. Accordingly, there is a need for a differential input pair using ambipolar transistors.
Some conventional circuits are: U.S. Patent Pre-Grant Publ. No. 2008/0290941; and Yang et al., “Triple-Mode Single-Transistor Graphene Amplifier and Its Applications,” ACS Nano, Vol. 4, No. 10, Oct. 12, 2010, pp. 5532-5538.